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  1. A Row-Parallel 88 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation
  2. Hardware Variability-Aware Duty Cycling for Embedded Sensors
  3. Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT
  4. A Best-First Soft/Hard Decision Tree Searching MIMO Decoder for a 4 4 64-QAM System
  5. A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration
  6. Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency Multiplier
  7. Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
  8. Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops
  9. ZeROA: Zero Clock Skew Rotary Oscillatory Array
  10. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
  11. Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
  12. A Novel Programmable Parallel CRC Circuit
  13. High-Speed Parallel Architectures for Linear Feedback Shift Registers
  14. Location-Based TDMA MAC for Reliable Aeronautical Communications
  15. Outage-Optimal TDMA Based Scheduling in Relay-Assisted MIMO Cellular Networks
  16. Two-User Gaussian Interference Channel with Finite Constellation Input and FDMA

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